1. Field of the Invention
This invention relates to electronics systems. Specifically, the present invention relates to electronic circuits.
2. Description of the Related Art
A variety of digital devices are implemented in electronic systems. The digital devices include inputs, logic devices, storage devices, clocks, outputs, etc. Many digital devices are implemented with a master-slave architecture. In a master-slave architecture, the operation of the slave component(s) are often based on the operation of at least one master component.
One conventional type of master-slave architecture is a master-slave latch. A master-slave latch (i.e., differential master-slave latch) includes at least one input port and at least two output ports. The output ports typically produce complimentary outputs. For example if a first output Q produces a logical 1 the second output Qn will produce a logical 0.
FIG. 1 displays a differential architecture. An input node is shown as 100. A pass gate 102 is positioned in series with the input node 100. The pass gate 102 is controlled by a master clock 103. A storage node 104 is positioned in series with the pass gate 102. An inverter 114 is coupled to the storage node 104. A pass gate 108, a storage node 106 and an inverter 115 are each positioned in series. The pass gate 108 is controlled by a slave clock 109. An output node Q shown as 116 is in series with the inverter 115.
A pass gate 112 is positioned on the output of the storage node 104. A storage node 110 and an inverter 118 are in series with the pass gate 112. A slave clock 111 controls the pass gate 112. A complimentary output node Qn is shown as 120. In this embodiment, the slave clocks 109 and 111 are the same clock.
During operation the master clock 103 operates pass device 102 and the slave clock (109 and 111) operates pass devices 108 and 112 respectively. As input is applied to node 100. The pass device 102 operates under control of the master clock 103. When the master clock 103 goes high, the data applied to input node 100 propagates to the storage node 104.
When the master clock 103 goes low that data is held by the master storage node 104. When the slave clock (109, 111) goes high, pass devices 108 and 112 allow data to pass. The data stored in storage node 104 propagates through inverter 114, through pass device 108 to storage node 106 and through pass device 112 to storage node 110. As a result of inverter 114 each individual storage nodes 106 and 110 will store an opposite value.
When the slave clock (109, 111) goes low, the two values stored in the storage nodes 106 and 110 are held independently of each other and propagated to the output Q 116 and the compliment of the output Qn 120. The data is then inverted using inverters 115 and 118, respectively and output at output node Q 116 and the compliment of output node Qn 120.
The problem with the foregoing structure is that on power-up the slave clock (109, 111) may remain at low voltage after the power is applied and it is possible and even likely that the storage nodes (106, 110) may initially power-up in the same state. The same values stored in storage node 106 and storage node 110 will drive either a pair of logical ones or a pair of logical zeros out of the output node Q 116 and the compliment of the output node Qn 120. Given that this circuit is a differential circuit this will cause a problem for any downstream circuits that may be sensitive to non-complimentary inputs, since the differential circuit is initially not producing a differential output.
Thus, there is a need for a differential circuit that is designed to assure a differential output on power-up. There is a need for a differential circuit that is designed to assure a differential output during all phases of operation.